EPC22C20N vs EPC2CC20N Comparison
Detailed side-by-side comparison of EPC22C20N by Altera and EPC2CC20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC22C20N | EPC2CC20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $11.40 | $10.85 |
| Manufacturer | Intel (formerly Altera) | β |
| Device Type | Configuration PROM for SRAM-based LUT FPGAs | β |
| Target FPGA Family | FLEX 10K, FLEX 6000, APEX 20K series | β |
| Configuration Interface | Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) | 16-bit parallel (FPP) / Passive Serial (PS) |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) | JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster |
| Supply Voltage | 3.3 V or 5 V | β |
| Package | 20-pin PLCC (J-lead) | PLCC-20 |
| Package Marking Code | EPC22C20N | β |
| Pin Count | 20 | β |
| Mounting Type | Surface Mount / Socket | Surface Mount (PLCC-20 socket compatible) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temp range] |
| Bitstream Capacity | [DATA_NEEDED: bitstream capacity in bits] | β |
| Configuration Time | [DATA_NEEDED: typical configuration time] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | β |
| Lifecycle Status | Obsolete (last-time-buy from Altera announced for legacy configuration devices) | β |
| Function | β | Configuration device for SRAM-based LUT FPGAs |
| Density | β | [DATA_NEEDED: bitstream density in bits] |
| Supply Voltage (VCC) | β | 3.3 V |
| In-System Programmable | β | Yes |
| Error Detection | β | 16-bit CRC on configuration frames |
| Configuration Modes Supported | β | FPP and PS (depends on host FPGA) |
| Cascadable | β | Yes (multiple EPC2 devices for larger bitstreams) |
| Open-Drain Status Pin | β | Yes (CONF_DONE / nSTATUS compatible) |
| MSL Level | β | [DATA_NEEDED: MSL rating] |