EPC2CC20N vs EPC21LC20 Comparison
Detailed side-by-side comparison of EPC2CC20N by Altera and EPC21LC20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC21LC20
EPC21LC20 - Altera 2 Mb Config PROM for SRAM-based LUT Devices | PLCC-20
EPC21LC20 β ActiveSpecification Comparison
| Parameter | EPC2CC20N | EPC21LC20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | Memory ICs |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.85 | $10.40 |
| Function | Configuration device for SRAM-based LUT FPGAs | β |
| Density | [DATA_NEEDED: bitstream density in bits] | 2 Mb (2,097,152 bits) |
| Package | PLCC-20 | β |
| Configuration Interface | 16-bit parallel (FPP) / Passive Serial (PS) | β |
| Supply Voltage (VCC) | 3.3 V | β |
| Programming Interface | JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster | IEEE 1149.1 (JTAG) |
| In-System Programmable | Yes | β |
| Error Detection | 16-bit CRC on configuration frames | β |
| Configuration Modes Supported | FPP and PS (depends on host FPGA) | β |
| Cascadable | Yes (multiple EPC2 devices for larger bitstreams) | β |
| Open-Drain Status Pin | Yes (CONF_DONE / nSTATUS compatible) | β |
| Operating Temperature | [DATA_NEEDED: industrial/commercial temp range] | β |
| Mounting Type | Surface Mount (PLCC-20 socket compatible) | Surface Mount (PLCC socket or solder) |
| MSL Level | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: confirm moisture sensitivity level] |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: confirm from Altera product page] |
| Memory Type | β | Serial Configuration PROM (Flash-based, in-system programmable) |
| Configuration Mode Supported | β | Serial (PS) for Altera SRAM-based LUT FPGAs |
| Maximum DCLK Frequency | β | 10 MHz |
| Access Time | β | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] |
| Program/Erase Endurance | β | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] |
| Operating Voltage (VCC) | β | 3.0 V to 3.6 V (3.3 V typical) |
| Standby Current | β | [DATA_NEEDED: ICCSB value] |
| Active Read Current | β | [DATA_NEEDED: ICC active current] |
| Operating Temperature (commercial) | β | 0 Β°C to +70 Β°C (LC suffix) |
| Operating Temperature (industrial) | β | [DATA_NEEDED: -40 to +85 Β°C for LI variant] |
| Package / Case | β | 20-pin PLCC (J-lead, JEDEC MS-018) |
| Lead-Free (Pb-free) | β | [DATA_NEEDED: confirm] |
| Compatible FPGA Families | β | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) |
| JTAG Boundary-Scan Compliant | β | Yes (IEEE Std 1149.1) |
| Data Width | β | 1 bit (serial DATA output) |