EPC2L20U-HAF480119C vs EPC2L20U Comparison
Detailed side-by-side comparison of EPC2L20U-HAF480119C by Intel and EPC2L20U by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC2L20U-HAF480119C
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C β Last Time BuySpecification Comparison
| Parameter | EPC2L20U-HAF480119C | EPC2L20U |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.75 | $10.55 |
| Memory Type | Configuration PROM (non-volatile) | β |
| Memory Size | 1.6 Mb | 1.6 Mbit |
| Target Device | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) | β |
| Core Supply Voltage | 3.3 V | β |
| I/O Tolerance | 5 V tolerant | β |
| Configuration Modes | Serial (1-bit), Parallel (8-bit FPP), JTAG | β |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | Yes (IEEE Std 1149.1 boundary scan) |
| Programmability | In-system programmable via JTAG | In-system programmable via IEEE 1532 / JTAG |
| Cascade Support | Yes (multi-PROM chains for larger FPGAs) | β |
| Configuration Clock Range | 10 MHz to 40 MHz | β |
| Bitstream Compression Support | Yes (Cyclone/Stratix compressed bitstreams) | β |
| Package | PLCC-20 | 20-PLCC (PLCC-20) |
| Mounting Type | Surface Mount / Socketed | Surface Mount / Socket |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Supply Voltage (VCC) | β | 3.0 V to 3.6 V |
| Interface Type | β | Serial configuration (DCLK/DATA0) |
| Supported FPGAs | β | APEX II, APEX 20K, Mercury, Stratix, Cyclone, ACEX 1K |
| Configuration Mode | β | Single + Cascade (multi-PROM daisy chain) |
| Compression Support | β | Yes (FPGA decompresses bitstream) |
| Operating Temperature | β | -40C to +85C (industrial) |
| Pin Count | β | 20 |
| MSL Level | β | [DATA_NEEDED: MSL level] |