EPF10K30ETC144-3 vs EPF10K30ETI144-3 Comparison

Detailed side-by-side comparison of EPF10K30ETC144-3 by Altera and EPF10K30ETI144-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPF10K30ETC144-3

EPF10K30ETC144-3 - 30K FLEX 10KE FPGA, 144-LQFP | Altera/Intel

EPF10K30ETC144-3 βœ“ Active
Altera
EPF10K30ETI144-3

EPF10K30ETI144-3 - 30K FLEX-10KE FPGA 102 I/O | Intel / Altera

EPF10K30ETI144-3 Obsolete

Specification Comparison

Parameter EPF10K30ETC144-3 EPF10K30ETI144-3
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $35.20 $29.80
Manufacturer Altera (now Intel) β€”
Series FLEX 10KE FLEX-10KE
Family FLEX 10KE FLEX-10KE Embedded Programmable Logic Device
Logic Elements / Cells 1728 β€”
Typical Gates 30,000 β€”
Embedded Memory (bits) 24,576 β€”
Embedded Array Blocks (EABs) 13 6
Logic Array Blocks (LABs) 216 216
User I/O Count 102 β€”
Number of I/O Banks 8 β€”
Core Voltage 2.5 V β€”
I/O Standards Supported LVTTL, LVCMOS, PCI (via MultiVolt) β€”
Speed Grade -3 β€”
Max Internal Frequency 200 MHz β€”
Process Technology 0.22 Β΅m CMOS SRAM β€”
Package 144-pin LQFP (TQFP) 144-LQFP (LFQFP)
Mounting Type Surface Mount Surface Mount (Gull Wing)
Operating Temperature (Commercial) 0 Β°C to +70 Β°C β€”
Configuration Mode Passive Serial / Active Serial / JTAG β€”
Configuration Voltage 5.0 V (EPC) / 2.5 V (core) β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] Non-Compliant (Sn/Pb lead finish)
Lead-Free [DATA_NEEDED: lead-free reflow compatibility] β€”
Logic Elements β€” 1728
Embedded RAM β€” 24,576 bits
Maximum User I/O β€” 102
Maximum Equivalent Gates β€” 119,000
Pin-to-Pin Delay (Speed Grade) β€” 12.5 ns
Supply Voltage (Core) β€” 2.5 V / 3.3 V
I/O Voltage Tolerance β€” 5.0 V / 3.3 V / 2.5 V (multi-volt)
Operating Temperature β€” -40C to +85C (Industrial)
Package Height β€” 1.6 mm
Lead Finish β€” Tin/Lead (Sn/Pb)
Configuration Method β€” SRAM (volatile) + JTAG IEEE 1149.1

Datasheets & Resources

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