EPF8282ALC84-3 vs EPF8636ALC84-4 Comparison

Detailed side-by-side comparison of EPF8282ALC84-3 by Altera and EPF8636ALC84-4 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPF8282ALC84-3

EPF8282ALC84-3 - FLEX 8000 FPGA 2.5K Gates 68 I/O 84-PLCC | Altera

EPF8282ALC84-3 Obsolete
Altera
EPF8636ALC84-4

EPF8636ALC84-4 - FLEX 8000 FPGA, 504 Cells, 84-PLCC | Intel / Altera

EPF8636ALC84-4 Obsolete

Specification Comparison

Parameter EPF8282ALC84-3 EPF8636ALC84-4
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.85 $24.30
Product Family FLEX 8000 β€”
Product Type FPGA - Field Programmable Gate Array β€”
Usable Gates 2,500 β€”
Logic Cells 208 β€”
Logic Array Blocks (LABs) 26 β€”
User I/Os 68 β€”
Maximum Operating Frequency 125 MHz 125 MHz
Supply Voltage (Core) 5 V 5.0 V
I/O Voltage Support 3.3 V or 5.0 V (MultiVolt) β€”
Technology 0.42 Β΅m CMOS, SRAM-based β€”
Configuration Method Serial (EPC1/EPC2 EPROM) - SRAM, in-circuit reconfigurable Serial (EPC1/EPC1064/EPC1213/EPC1441) or parallel EPROM
Package Type 84-pin PLCC (Plastic Leaded Chip Carrier, J-Lead) β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial) 0 Β°C to +70 Β°C (Commercial)
Mounting Type Surface Mount / Through-Hole (J-Lead, socketable) Surface Mount / Socket
RoHS Status [DATA_NEEDED: RoHS status - legacy part likely non-RoHS, confirm] Non-compliant (legacy PLCC, lead-bearing)
Speed Grade -3 (production timing bin) -4
Family β€” FLEX 8000
Number of Logic Cells β€” 504
Number of Logic Array Blocks (LABs) β€” 63
Maximum Usable Gates β€” 6,000
Number of User I/O Pins β€” 68
Process Technology β€” 0.42 Β΅m CMOS SRAM
I/O Voltage (84-pin PLCC) β€” 5.0 V only (3.3 V I/O NOT supported on this package)
Operating Current (typical) β€” 10 mA
Package β€” 84-Pin PLCC (J-Lead)
Configuration Memory Type β€” Volatile SRAM (requires boot device)
Boundary Scan β€” IEEE 1149.1 (JTAG)

Datasheets & Resources

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