EPF8820ARC208-3N vs EPF8820ARC208-3 Comparison

Detailed side-by-side comparison of EPF8820ARC208-3N by Altera and EPF8820ARC208-3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPF8820ARC208-3N

EPF8820ARC208-3N - FLEX 8000 FPGA, 672 LEs, 125MHz, 208-RQFP | Altera

EPF8820ARC208-3N Obsolete
Intel
EPF8820ARC208-3

EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera

EPF8820ARC208-3 Obsolete

Specification Comparison

Parameter EPF8820ARC208-3N EPF8820ARC208-3
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $85.00 $62.00
Family FLEX 8000 FLEX 8000 (EPF8820)
Device Type Field Programmable Gate Array (FPGA) β€”
Usable Gates 8,000 8,000
Logic Elements 672 β€”
Logic Array Blocks (LABs) 672 / 10 β‰ˆ 67 LABs β€”
FlipFlops 152 β€”
Maximum Operating Frequency 125 MHz 125 MHz
Propagation Delay 5 ns (speed grade -3) β€”
Process Technology 0.42 Β΅m CMOS 0.42 Β΅m CMOS
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5 V nominal) β€”
User I/O Voltage 3.3 V or 5 V (selectable) β€”
User I/O Count 152 β€”
Package 208-pin RQFP / BFQFP Exposed Pad (28x28 mm) β€”
Configuration Memory SRAM (volatile, external configuration device required) SRAM (volatile)
Configuration Devices EPC1, EPC1213, EPC1064, EPC1441 β€”
In-System Reconfigurability Yes (ICR via configuration device or controller) β€”
JTAG Support Yes (boundary-scan + configuration) β€”
Speed Grade -3 β€”
RoHS Status unknown [DATA_NEEDED: RoHS status]
Series β€” FLEX 8000
Logic Cells / Elements β€” 672
Registers β€” 152
Supply Voltage (VCC) β€” 4.75 V to 5.25 V
Package / Case β€” 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm)
Supplier Device Package β€” 208-RQFP (28x28)
Mounting Type β€” Surface Mount
Packaging β€” Tray
Operating Temperature Range β€” [DATA_NEEDED: operating temperature range]
In-Circuit Reconfigurability (ICR) β€” Yes (via external configuration devices)
Boundary-Scan Test β€” JTAG (IEEE 1149.1)
I/O Tolerance β€” 3.3 V / 5 V
Clock Networks β€” 4 dedicated low-skew global clocks
Lead-Free / Finish β€” [DATA_NEEDED: lead-free finish]

Datasheets & Resources

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