EPM240GT100C5N vs EPM240T100C5 Comparison

Detailed side-by-side comparison of EPM240GT100C5N by Altera and EPM240T100C5 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM240GT100C5N EPM240T100C5
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $9.20 $6.20
Family MAX II MAX II
Series EPM240 β€”
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Logic Elements (LEs) 240 β€”
Macrocells 192 192
User I/Os 80 β€”
Pin-to-Pin Delay (tPD) 4.7 ns β€”
User Flash Memory (UFM) 8 Kbits β€”
Core Supply Voltage (VCCINT) 2.5 V or 3.3 V β€”
I/O Supply Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V β€”
Operating Temperature 0C to +85C (Commercial) 0C to +85C (Commercial)
Package 100-pin TQFP (T100) 100-pin TQFP (14 mm Γ— 14 mm Γ— 1 mm)
Mounting Type Surface Mount β€”
Programmable Type In-System Programmable (ISP) via JTAG β€”
Configuration Memory Non-volatile Flash (instant-on) β€”
MSL Level 3 β€”
RoHS Status Compliant β€”
Maximum User I/O Pins β€” 80
Logic Elements β€” 240
Non-volatile Memory β€” 8 Kbits (embedded Flash)
Pin-to-Pin Logic Delay (tPD1) β€” 4.7 ns
Maximum Internal Frequency β€” 201.1 MHz
Process Technology β€” 0.18 Β΅m, 6-layer metal Flash
Core Supply Voltage β€” 2.5 V / 3.3 V
I/O Voltage Support β€” 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O)
I/O Banks β€” 4
Programming Interface β€” JTAG (IEEE 1149.1) / ISP
Chip-wide Output Enable β€” DEV_OE pin

Datasheets & Resources

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