EPM240T100A5N vs EPM240T100C5N Comparison
Detailed side-by-side comparison of EPM240T100A5N by Altera and EPM240T100C5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM240T100A5N
EPM240T100A5N - 192-Macrocell MAX II CPLD, 100-TQFP | Intel / Altera
EPM240T100A5N β ActiveAltera
EPM240T100C5N
EPM240T100C5N - 240-LE MAX II CPLD, 100-TQFP | Intel / Altera
EPM240T100C5N β ActiveSpecification Comparison
| Parameter | EPM240T100A5N | EPM240T100C5N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.05 | $4.32 |
| Family | MAX II | MAX II |
| Macro Cells | 192 | β |
| Logic Elements (LE) | 240 | 240 |
| User I/O Count | 80 | β |
| Pin-to-Pin Logic Delay (tPD) | 4.7 ns | β |
| Maximum Internal Frequency | 201.1 MHz | 201.1 MHz |
| Supply Voltage | 2.5 V / 3.3 V | β |
| I/O Bank Count | 4 (multi-voltage) | β |
| Process Technology | 0.18 Β΅m | 0.18 Β΅m, 6-layer-metal flash |
| Configuration Memory | On-chip Flash (instant-on) | Internal non-volatile flash (instant-on) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | IEEE 1149.1 JTAG (in-system programmable) |
| Package | 100-pin TQFP (14 x 14 x 1.0 mm) | 100-pin TQFP (T100) |
| Operating Temperature | 0C to +85C (commercial, "A5N" suffix) | 0 Β°C to +85 Β°C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant (Pb-free) | Compliant (lead-free, per distributor listings) |
| Equivalent Macrocells | β | 192 |
| User Flash Memory | β | 8 Kbits |
| Maximum User I/O | β | 80 |
| Propagation Delay (tPD) | β | 4.7 ns (speed grade 5) |
| Number of I/O Banks | β | 4 |
| Core Supply Voltage | β | 2.5 V / 3.3 V |
| MultiVolt I/O Support | β | 1.5 V, 1.8 V, 2.5 V, 3.3 V |