EPM240T100C4 vs EPM240T100C4N Comparison
Detailed side-by-side comparison of EPM240T100C4 by Intel and EPM240T100C4N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM240T100C4
EPM240T100C4 - MAX II 192-MacroCell CPLD, 4.7ns TQFP-100 | Intel
EPM240T100C4 β ActiveAltera
EPM240T100C4N
EPM240T100C4N - MAX II 192-MacroCell CPLD, 4.7ns TQFP-100 | Altera
EPM240T100C4N β ActiveSpecification Comparison
| Parameter | EPM240T100C4 | EPM240T100C4N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $6.10 |
| Series | MAX II | β |
| Programmable Type | In System Programmable | In-System Programmable (Flash) |
| Number of Macrocells | 192 | β |
| Number of Logic Elements/Blocks | 240 | β |
| Number of User I/O | 80 | β |
| Maximum Propagation Delay (tPD) | 4.7 ns | β |
| Internal Supply Voltage | 2.5 V / 3.3 V | β |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) | β |
| Process Technology | 0.18 Β΅m CMOS, non-volatile Flash | 0.18 Β΅m |
| User Flash Memory | 8 Kbits (typical) | β |
| Package / Case | 100-pin TQFP | 100-TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 Β°C to +85 Β°C (TJ, commercial) | 0 Β°C to +85 Β°C (commercial, 'C' suffix) |
| Programming Interface | JTAG (IEEE 1149.1) - ISP | β |
| Supplier Device Package | 100-TQFP (16 Γ 16 mm, 0.5 mm pitch) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free, 'N' suffix) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Family | β | MAX II |
| Device | β | EPM240 |
| Macro Cells | β | 192 |
| Logic Elements | β | 240 |
| Propagation Delay (tPD) | β | 4.7 ns (max) |
| Maximum Frequency | β | 247.5 MHz |
| User I/O | β | 80 |
| Supply Voltage - Internal | β | 2.5 V / 3.3 V |
| I/O Voltage (MultiVolt) | β | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| JTAG Support | β | IEEE 1149.1 boundary-scan |