EPM240T100C4N vs EPM240T100C5 Comparison
Detailed side-by-side comparison of EPM240T100C4N by Altera and EPM240T100C5 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM240T100C4N
EPM240T100C4N - MAX II 192-MacroCell CPLD, 4.7ns TQFP-100 | Altera
EPM240T100C4N β ActiveAltera
EPM240T100C5
EPM240T100C5 - MAX II CPLD, 192 Macrocells, 100-TQFP | Altera
EPM240T100C5 β ActiveSpecification Comparison
| Parameter | EPM240T100C4N | EPM240T100C5 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.10 | $6.20 |
| Family | MAX II | MAX II |
| Device | EPM240 | β |
| Macro Cells | 192 | β |
| Logic Elements | 240 | 240 |
| Propagation Delay (tPD) | 4.7 ns (max) | β |
| Maximum Frequency | 247.5 MHz | β |
| User I/O | 80 | β |
| Supply Voltage - Internal | 2.5 V / 3.3 V | β |
| I/O Voltage (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | β |
| Process Technology | 0.18 Β΅m | 0.18 Β΅m, 6-layer metal Flash |
| Programmable Type | In-System Programmable (Flash) | β |
| Package / Case | 100-TQFP | β |
| Mounting Type | Surface Mount | β |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial, 'C' suffix) | 0C to +85C (Commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan | β |
| RoHS Status | Compliant (lead-free, 'N' suffix) | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 192 |
| Maximum User I/O Pins | β | 80 |
| Non-volatile Memory | β | 8 Kbits (embedded Flash) |
| Pin-to-Pin Logic Delay (tPD1) | β | 4.7 ns |
| Maximum Internal Frequency | β | 201.1 MHz |
| Core Supply Voltage | β | 2.5 V / 3.3 V |
| I/O Voltage Support | β | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| I/O Banks | β | 4 |
| Package | β | 100-pin TQFP (14 mm Γ 14 mm Γ 1 mm) |
| Programming Interface | β | JTAG (IEEE 1149.1) / ISP |
| Chip-wide Output Enable | β | DEV_OE pin |