EPM240T100C5 vs EPM240GT100C5N Comparison
Detailed side-by-side comparison of EPM240T100C5 by Altera and EPM240GT100C5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM240T100C5 | EPM240GT100C5N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.20 | $9.20 |
| Family | MAX II | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Maximum User I/O Pins | 80 | β |
| Logic Elements | 240 | β |
| Non-volatile Memory | 8 Kbits (embedded Flash) | β |
| Pin-to-Pin Logic Delay (tPD1) | 4.7 ns | β |
| Maximum Internal Frequency | 201.1 MHz | β |
| Process Technology | 0.18 Β΅m, 6-layer metal Flash | β |
| Core Supply Voltage | 2.5 V / 3.3 V | β |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) | β |
| I/O Banks | 4 | β |
| Package | 100-pin TQFP (14 mm Γ 14 mm Γ 1 mm) | 100-pin TQFP (T100) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | β |
| Operating Temperature | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| Chip-wide Output Enable | DEV_OE pin | β |
| Series | β | EPM240 |
| Logic Elements (LEs) | β | 240 |
| User I/Os | β | 80 |
| Pin-to-Pin Delay (tPD) | β | 4.7 ns |
| User Flash Memory (UFM) | β | 8 Kbits |
| Core Supply Voltage (VCCINT) | β | 2.5 V or 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Mounting Type | β | Surface Mount |
| Programmable Type | β | In-System Programmable (ISP) via JTAG |
| Configuration Memory | β | Non-volatile Flash (instant-on) |
| MSL Level | β | 3 |
| RoHS Status | β | Compliant |