EPM3032A-TC44-10N vs EPM3032ALC-44-10N Comparison
Detailed side-by-side comparison of EPM3032A-TC44-10N by Altera and EPM3032ALC-44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3032ALC-44-10N - MAX 3000A CPLD, 32MC, 10ns, 44-PLCC | Altera
EPM3032ALC-44-10N β Last Time BuySpecification Comparison
| Parameter | EPM3032A-TC44-10N | EPM3032ALC-44-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.40 | $5.45 |
| Manufacturer | Altera (now Intel) | β |
| Series | MAX 3000A | β |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 32 | 32 |
| Usable Gates | 600 | β |
| Logic Elements / LABs | 2 Logic Array Blocks | β |
| User I/O Pins | 34 | 34 |
| Number of Pins | 44 | β |
| Package | 44-pin TQFP | 44-pin PLCC |
| Pin-to-Pin Delay (tPD) | 10 ns (commercial speed grade) | β |
| Counter Frequency (fCNT) | up to 227.3 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| Programming Technology | EEPROM (in-system programmable via JTAG / IEEE 1532) | β |
| Output Enables | 6 global OE signals | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial, -N suffix) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket compatible) |
| Process Technology | CMOS EEPROM | β |
| Product Type | β | CPLD - Complex Programmable Logic Device |
| Logic Array Blocks (LABs) | β | 2 |
| Gates | β | 600 |
| Pin-to-Pin Logic Delay (tPD) | β | 4.5 ns |
| Counter Frequency (max) | β | 227.3 MHz |
| Speed Grade | β | -10 (10 ns) |
| Supply Voltage (Core) | β | 3.3 V |
| I/O Logic Compatibility | β | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programming Interface | β | JTAG (IEEE Std. 1149.1) / ISP (IEEE Std. 1532) |
| Configuration Memory | β | EEPROM (non-volatile) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |