EPM3032ATI44-10N vs EPM3032ALC44-10N Comparison
Detailed side-by-side comparison of EPM3032ATI44-10N by Intel and EPM3032ALC44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3032ATI44-10N
EPM3032ATI44-10N - 600-Gate 32-Macrocell 3.3V CPLD | Intel / Altera
EPM3032ATI44-10N ObsoleteAltera
EPM3032ALC44-10N
EPM3032ALC44-10N - 32 Macrocell CPLD, 10ns, 44-PLCC | Altera
EPM3032ALC44-10N NrndSpecification Comparison
| Parameter | EPM3032ATI44-10N | EPM3032ALC44-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.10 | $0.94 |
| Family | MAX 3000A | MAX 3000A |
| Logic Capacity | 600 usable gates | β |
| Number of Macrocells | 32 | β |
| Number of User I/Os | 34 | β |
| Package / Case | TQFP-44 (10x10 mm, 0.8 mm pitch) | β |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | 3.3 V |
| MultiVolt I/O Interface | 5.0 V, 3.3 V, 2.5 V compatible | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Counter Frequency (fCNT) | 103.1 MHz | β |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | β |
| Programmability | In-System Programmable (ISP) via IEEE Std. 1149.1 JTAG | β |
| ISP Standard | IEEE Std. 1532 compliant | β |
| Configuration Memory | Non-volatile EEPROM | β |
| Hot-Socketing Support | Yes | β |
| Operating Temperature | -40C to +85C (industrial, 'I' grade) | [DATA_NEEDED: industrial/commercial range] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | RoHS Non-Compliant (contains lead) | [DATA_NEEDED: compliant or non-compliant] |
| Lead-Free Status | Contains lead | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Gates | β | 600 gates |
| Macrocells | β | 32 |
| Logic Array Blocks (LABs) | β | 2 |
| User I/O Pins | β | 34 |
| Propagation Delay (tPD) | β | 10 ns |
| Internal fMAX | β | 103.1 MHz |
| I/O Voltage (VCCIO) | β | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) |
| Technology | β | CMOS EEPROM-based |
| In-System Programmability | β | Yes, via IEEE 1149.1 JTAG |
| ISP Standard Compliance | β | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | β | Yes, IEEE 1149.1 compliant |
| Package | β | 44-pin PLCC (J-Lead, surface mount) |