EPM3064ALC44-10N vs EPM3064ATI44-10N Comparison

Detailed side-by-side comparison of EPM3064ALC44-10N by Altera and EPM3064ATI44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ALC44-10N EPM3064ATI44-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $4.25 $3.95
Product Family MAX 3000A β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 64 64
Logic Array Blocks (LABs) 4 β€”
User I/O Pins 34 β€”
Usable Gates 1,250 1250
Propagation Delay (tPD) 10 ns β€”
Maximum Counter Frequency 227.3 MHz β€”
Supply Voltage (VCCINT) 3.0 V to 3.6 V β€”
I/O Bank Voltage (VCCIO) 3.0 V to 3.6 V (MultiVolt) β€”
Configuration Memory CMOS EEPROM β€”
In-System Programmability Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) β€”
Package 44-pin PLCC (LC44) 44-pin TQFP
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
Operating Temperature [DATA_NEEDED: commercial / industrial grade] -40C to +85C (Industrial, "N" suffix)
RoHS Status Compliant Non-Compliant (per digchip datasheet excerpt)
Open-Drain Output Option Yes (per I/O pin) β€”
Output Slew-Rate Control Programmable β€”
Family β€” MAX 3000A
Product Type β€” CPLD (Complex Programmable Logic Device)
User I/Os β€” 34
Dedicated Inputs β€” 4
Logic Blocks β€” 4
Pin-to-Pin Delay β€” 10 ns (-10 speed grade)
Maximum Frequency (fMAX) β€” 100 MHz
Programmable Type β€” In-System Programmable (EEPROM)
ISP Interface β€” IEEE Std. 1149.1 (JTAG)
ISP Standard Compliance β€” IEEE Std. 1532
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 3.3 V or 2.5 V (MultiVolt)
Process Technology β€” CMOS EEPROM
Boundary-Scan Test β€” Built-in (JTAG)
Lead-Free Status β€” Contains Lead (per digchip datasheet excerpt)

Datasheets & Resources

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