EPM3064ALC44-7N vs EPM3064ATC44-7N Comparison

Detailed side-by-side comparison of EPM3064ALC44-7N by Intel and EPM3064ATC44-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ALC44-7N EPM3064ATC44-7N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $3.95 $2.30
Family MAX 3000A MAX 3000A
Logic IC Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 64 β€”
Logic Array Blocks (LABs) 2 β€”
Usable Gates 1,250 1,250
Number of User I/O Pins 34 β€”
Pin-to-Pin Delay (tPD) 7.5 ns 7.5 ns
Maximum Frequency 135.1 MHz β€”
Core Technology CMOS EEPROM β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Tolerance 5 V-tolerant β€”
In-System Programmability Yes (IEEE Std 1149.1 JTAG) β€”
Package 44-pin PLCC 44-pin TQFP
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
Operating Temperature 0C to +70C (commercial) 0Β°C to +85Β°C (commercial)
RoHS Status [DATA_NEEDED: RoHS status] Compliant
Programming Software Quartus II / Quartus Prime (legacy MAX+PLUS II supported) β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 64
Logic Array Blocks β€” 2
User I/O Pins β€” 34
Number of Pins β€” 44
Speed Grade β€” -7 (7.5 ns pin-to-pin delay)
Maximum Counter Frequency β€” 192.3 MHz (-7 grade)
Supply Voltage (VCC) β€” 3.3 V
MultiVolt I/O β€” 1.8 V / 2.5 V / 3.3 V
Programmability β€” EEPROM, in-system programmable (ISP)
JTAG Interface β€” IEEE Std. 1149.1 compliant
ISP Standard β€” IEEE Std. 1532 compliant
Boundary-Scan Test (BST) β€” Built-in, JTAG-driven

Datasheets & Resources

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