EPM3064AT100-10N vs EPM3064ATC100-10N Comparison
Detailed side-by-side comparison of EPM3064AT100-10N by Altera and EPM3064ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC100-10N - MAX 3000A CPLD, 64 Macrocells, 66 I/O | Altera
EPM3064ATC100-10N β ActiveSpecification Comparison
| Parameter | EPM3064AT100-10N | EPM3064ATC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.45 | $2.43 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 2 |
| Usable Gates | 1,250 | 1,250 |
| User I/O Pins | 66 | β |
| Speed Grade | -10 (10 ns pin-to-pin delay) | β |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V (3.0 V to 3.6 V) |
| I/O Bank Voltage | 3.3 V | β |
| 5 V Tolerant Inputs | Yes (via clamping diodes) | β |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM |
| Programming Interface | JTAG (IEEE Std. 1149.1) with pin-locking | β |
| ISP Compliance | IEEE Std. 1532 | β |
| Boundary-Scan Test (BST) | IEEE Std. 1149.1 compliant | Yes - JTAG compliant |
| Package | TQFP-100 (T100), 14 mm x 14 mm | 100-pin TQFP |
| Operating Temperature (Commercial) | 0C to +70C | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Compliant (lead-free) |
| Lead-Free | [DATA_NEEDED: lead-free finish] | β |
| Maximum User I/O Pins | β | 66 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| In-System Programmability | β | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Program/Erase Cycles | β | 100 minimum |
| MultiVolt I/O | β | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |
| Operating Temperature | β | 0C to +70C (commercial) |
| Mounting Type | β | Surface Mount |