EPM3064AT100-10N vs EPM3064ATI100-10N Comparison
Detailed side-by-side comparison of EPM3064AT100-10N by Altera and EPM3064ATI100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064AT100-10N
EPM3064AT100-10N - MAX 3000A CPLD, 64 Macrocells, TQFP-100 | Intel
EPM3064AT100-10N NrndAltera
EPM3064ATI100-10N
EPM3064ATI100-10N - MAX 3000A CPLD, 64-Macrocell, 100-TQFP | Altera
EPM3064ATI100-10N β ActiveSpecification Comparison
| Parameter | EPM3064AT100-10N | EPM3064ATI100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.45 | $9.80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Usable Gates | 1,250 | 1,250 |
| User I/O Pins | 66 | β |
| Speed Grade | -10 (10 ns pin-to-pin delay) | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Bank Voltage | 3.3 V | β |
| 5 V Tolerant Inputs | Yes (via clamping diodes) | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| Programming Interface | JTAG (IEEE Std. 1149.1) with pin-locking | β |
| ISP Compliance | IEEE Std. 1532 | β |
| Boundary-Scan Test (BST) | IEEE Std. 1149.1 compliant | β |
| Package | TQFP-100 (T100), 14 mm x 14 mm | 100-pin TQFP (industrial) |
| Operating Temperature (Commercial) | 0C to +70C | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | RoHS Non-Compliant |
| Lead-Free | [DATA_NEEDED: lead-free finish] | β |
| Programmable Type | β | In-System Programmable (ISP) via IEEE 1149.1 JTAG |
| Technology | β | CMOS EEPROM |
| User I/O | β | 66 |
| Supply Voltage (Core / I/O) | β | 3.3 V |
| Pin-to-Pin Delay (tPD) | β | 10 ns (-10 speed grade) |
| Maximum Internal Frequency | β | 227.3 MHz (counter) |
| Operating Temperature | β | -40 C to +85 C (industrial) |
| JTAG (IEEE 1149.1) | β | Yes |
| PCI Compliance | β | PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) |
| MultiVolt I/O | β | Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing |
| Lead-Free Status | β | Contains Lead |