EPM3064ATC100-10 vs EPM3064AT100-10N Comparison

Detailed side-by-side comparison of EPM3064ATC100-10 by Altera and EPM3064AT100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC100-10 EPM3064AT100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $2.85 $5.45
Family MAX 3000A MAX 3000A
Logic Gates 1250 gates β€”
Macrocells 64 64
Logic Array Blocks 2 β€”
User I/O Pins 34 66
Package TQFP-100 (100-pin Thin Quad Flat Pack) TQFP-100 (T100), 14 mm x 14 mm
Propagation Delay (tPD) 10 ns β€”
Supply Voltage (VCCINT) 3.3 V 3.3 V
Process Technology CMOS EEPROM β€”
In-System Programmability IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant β€”
Global Clock Signals 2 (with optional inversion) β€”
Output Enable Signals 6 or 10 pin- or logic-driven β€”
Output Slew-Rate Control Programmable β€”
Operating Temperature Grade Commercial β€”
MultiVolt I/O Support 1.5V / 1.8V / 2.5V / 3.3V interfaces β€”
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance status]
Device Type β€” CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) β€” 4
Usable Gates β€” 1,250
Speed Grade β€” -10 (10 ns pin-to-pin delay)
I/O Bank Voltage β€” 3.3 V
5 V Tolerant Inputs β€” Yes (via clamping diodes)
Configuration Memory β€” EEPROM (non-volatile)
Programming Interface β€” JTAG (IEEE Std. 1149.1) with pin-locking
ISP Compliance β€” IEEE Std. 1532
Boundary-Scan Test (BST) β€” IEEE Std. 1149.1 compliant
Operating Temperature (Commercial) β€” 0C to +70C
Lead-Free β€” [DATA_NEEDED: lead-free finish]

Datasheets & Resources

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