EPM3064ATC100-10 vs EPM3064ATC100-10NA Comparison

Detailed side-by-side comparison of EPM3064ATC100-10 by Altera and EPM3064ATC100-10NA by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC100-10 EPM3064ATC100-10NA
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Active
Stock Status In Stock In Stock
Unit Price (USD) $2.85 $4.65
Family MAX 3000A MAX 3000A
Logic Gates 1250 gates β€”
Macrocells 64 64
Logic Array Blocks 2 β€”
User I/O Pins 34 β€”
Package TQFP-100 (100-pin Thin Quad Flat Pack) TQFP-100 (0.5 mm pitch)
Propagation Delay (tPD) 10 ns β€”
Supply Voltage (VCCINT) 3.3 V 3.3 V
Process Technology CMOS EEPROM β€”
In-System Programmability IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant β€”
Global Clock Signals 2 (with optional inversion) β€”
Output Enable Signals 6 or 10 pin- or logic-driven β€”
Output Slew-Rate Control Programmable β€”
Operating Temperature Grade Commercial β€”
MultiVolt I/O Support 1.5V / 1.8V / 2.5V / 3.3V interfaces β€”
RoHS Status [DATA_NEEDED: RoHS compliance] β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
User I/Os β€” 66
Usable Gates β€” 1,250
Logic Array Blocks (LABs) β€” 4
Pin-to-Pin Delay (tPD) β€” 10 ns
Maximum Operating Frequency β€” [DATA_NEEDED: fMAX in MHz]
MultiVolt I/O Voltages β€” 2.5 V / 3.3 V / 5.0 V
Configuration Memory β€” Non-volatile EEPROM
In-System Programming β€” IEEE Std. 1532 compliant
Boundary-Scan Test β€” IEEE Std. 1149.1 (JTAG)
Operating Temperature β€” 0C to +70C (commercial)
Lead-Free / RoHS β€” Yes (NA suffix)

Datasheets & Resources

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