EPM3064ATC100-10N vs EPM3064ATC100-4 Comparison

Detailed side-by-side comparison of EPM3064ATC100-10N by Altera and EPM3064ATC100-4 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC100-10N EPM3064ATC100-4
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $2.43 $5.20
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (EEPROM-based)
Macrocells 64 β€”
Logic Array Blocks (LABs) 2 2
Maximum User I/O Pins 66 34
Usable Gates 1,250 1,250 (range 600 to 10,000 across family)
Pin-to-Pin Delay (tPD) 10 ns 4.5 ns
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) β€”
In-System Programmability Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 β€”
Boundary-Scan Test (BST) Yes - JTAG compliant β€”
Configuration Memory Non-volatile EEPROM β€”
Program/Erase Cycles 100 minimum β€”
MultiVolt I/O Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant β€”
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option]
Package 100-pin TQFP 100-pin TQFP
Mounting Type Surface Mount Surface Mount
RoHS Status Compliant (lead-free) unknown
Macro Cells β€” 64
Counter Frequency (fCNT) β€” 227.3 MHz
Internal Performance β€” 222.2 MHz
Supply Voltage VCCINT β€” 3.3 V
I/O Voltage (MultiVolt) β€” 2.5 V / 3.3 V / 5.0 V
In-System Programming β€” Yes (IEEE 1149.1 JTAG)
Process Technology β€” CMOS EEPROM
Architecture β€” 5-level Altera MAX

Datasheets & Resources

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