EPM3064ATC100-10N vs EPM3064ATC100-7N Comparison

Detailed side-by-side comparison of EPM3064ATC100-10N by Altera and EPM3064ATC100-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC100-10N EPM3064ATC100-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $2.43 $6.10
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macrocells 64 64
Logic Array Blocks (LABs) 2 2
Maximum User I/O Pins 66 β€”
Usable Gates 1,250 up to 1,250
Pin-to-Pin Delay (tPD) 10 ns β€”
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) β€”
In-System Programmability Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 β€”
Boundary-Scan Test (BST) Yes - JTAG compliant β€”
Configuration Memory Non-volatile EEPROM β€”
Program/Erase Cycles 100 minimum β€”
MultiVolt I/O Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant β€”
Operating Temperature 0C to +70C (commercial) 0 Β°C to +70 Β°C (commercial)
Package 100-pin TQFP TQFP-100
Mounting Type Surface Mount Surface Mount
RoHS Status Compliant (lead-free) [DATA_NEEDED: confirmed RoHS status from manufacturer page]
User I/O Pins β€” 66
Propagation Delay (tPD) β€” 7.5 ns (pin-to-pin, -7 speed grade)
Maximum Internal Frequency β€” 166.7 MHz (-7 speed grade)
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 3.3 V or 2.5 V
Program Memory Technology β€” EEPROM (non-volatile)
In-System Programming β€” IEEE Std. 1149.1 (JTAG), IEEE Std. 1532

Datasheets & Resources

Browse All Products Create BOM Request Quote