EPM3064ATC100-10N vs EPM3064ATI100-10N Comparison

Detailed side-by-side comparison of EPM3064ATC100-10N by Altera and EPM3064ATI100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC100-10N EPM3064ATI100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $2.43 $9.80
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 64 64
Logic Array Blocks (LABs) 2 4
Maximum User I/O Pins 66 β€”
Usable Gates 1,250 1,250
Pin-to-Pin Delay (tPD) 10 ns 10 ns (-10 speed grade)
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) β€”
In-System Programmability Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 β€”
Boundary-Scan Test (BST) Yes - JTAG compliant β€”
Configuration Memory Non-volatile EEPROM β€”
Program/Erase Cycles 100 minimum β€”
MultiVolt I/O Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing
Operating Temperature 0C to +70C (commercial) -40 C to +85 C (industrial)
Package 100-pin TQFP 100-pin TQFP (industrial)
Mounting Type Surface Mount β€”
RoHS Status Compliant (lead-free) RoHS Non-Compliant
Programmable Type β€” In-System Programmable (ISP) via IEEE 1149.1 JTAG
Technology β€” CMOS EEPROM
User I/O β€” 66
Supply Voltage (Core / I/O) β€” 3.3 V
Maximum Internal Frequency β€” 227.3 MHz (counter)
JTAG (IEEE 1149.1) β€” Yes
PCI Compliance β€” PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades)
Lead-Free Status β€” Contains Lead

Datasheets & Resources

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