EPM3064ATC100-4 vs EPM3064ATC100-10N Comparison

Detailed side-by-side comparison of EPM3064ATC100-4 by Altera and EPM3064ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064ATC100-4

EPM3064ATC100-4 - 64-Macrocell CPLD, 4.5ns, 100-TQFP | Altera

EPM3064ATC100-4 Nrnd
Altera
EPM3064ATC100-10N

EPM3064ATC100-10N - MAX 3000A CPLD, 64 Macrocells, 66 I/O | Altera

EPM3064ATC100-10N βœ“ Active

Specification Comparison

Parameter EPM3064ATC100-4 EPM3064ATC100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Active
Stock Status In Stock In Stock
Unit Price (USD) $5.20 $2.43
Family MAX 3000A MAX 3000A
Device Type CPLD (EEPROM-based) CPLD (Complex Programmable Logic Device)
Macro Cells 64 β€”
Logic Array Blocks (LABs) 2 2
Usable Gates 1,250 (range 600 to 10,000 across family) 1,250
Maximum User I/O Pins 34 66
Pin-to-Pin Delay (tPD) 4.5 ns 10 ns
Counter Frequency (fCNT) 227.3 MHz β€”
Internal Performance 222.2 MHz β€”
Supply Voltage VCCINT 3.3 V β€”
I/O Voltage (MultiVolt) 2.5 V / 3.3 V / 5.0 V β€”
In-System Programming Yes (IEEE 1149.1 JTAG) β€”
Process Technology CMOS EEPROM β€”
Package 100-pin TQFP 100-pin TQFP
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] 0C to +70C (commercial)
RoHS Status unknown Compliant (lead-free)
Architecture 5-level Altera MAX β€”
Macrocells β€” 64
Supply Voltage (VCCINT) β€” 3.3 V (3.0 V to 3.6 V)
In-System Programmability β€” Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) β€” Yes - JTAG compliant
Configuration Memory β€” Non-volatile EEPROM
Program/Erase Cycles β€” 100 minimum
MultiVolt I/O β€” Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant

Datasheets & Resources

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