EPM3064ATC100-4N vs EPM3064ATC100-10N Comparison
Detailed side-by-side comparison of EPM3064ATC100-4N by Altera and EPM3064ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC100-4N
EPM3064ATC100-4N - MAX 3000A CPLD, 64 Macro, 66 I/O, 100-TQFP
EPM3064ATC100-4N NrndAltera
EPM3064ATC100-10N
EPM3064ATC100-10N - MAX 3000A CPLD, 64 Macrocells, 66 I/O | Altera
EPM3064ATC100-10N β ActiveSpecification Comparison
| Parameter | EPM3064ATC100-4N | EPM3064ATC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.60 | $2.43 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 64 | β |
| Logic Array Blocks | 2 | β |
| Usable Gates | 1,250 | 1,250 |
| User I/O Pins | 66 | β |
| Pin-to-Pin Delay (tPD) | 4.5 ns | 10 ns |
| Counter Frequency | 222.2 MHz (max) | β |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V (3.0 V to 3.6 V) |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | β |
| Package | 100-pin TQFP | 100-pin TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | β |
| ISP Standard | IEEE Std. 1532 | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Process Technology | CMOS EEPROM | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free) |
| Macrocells | β | 64 |
| Logic Array Blocks (LABs) | β | 2 |
| Maximum User I/O Pins | β | 66 |
| In-System Programmability | β | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | β | Yes - JTAG compliant |
| Configuration Memory | β | Non-volatile EEPROM |
| Program/Erase Cycles | β | 100 minimum |
| MultiVolt I/O | β | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |