EPM3064ATC100-7 vs EPM3064ATC-100-10N Comparison

Detailed side-by-side comparison of EPM3064ATC100-7 by Altera and EPM3064ATC-100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064ATC-100-10N EPM3064ATC-100-10N - 64-Macrocell MAX 3000A CPLD, 10ns | Altera

EPM3064ATC-100-10N - 64-Macrocell MAX 3000A CPLD, 10ns | Altera

EPM3064ATC-100-10N βœ“ Active

Specification Comparison

Parameter EPM3064ATC100-7 EPM3064ATC-100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $3.08 $2.20
Family MAX 3000A MAX 3000A
Usable Gates 1,250 β€”
Macrocells 64 β€”
Logic Array Blocks (LABs) 2 2
Maximum User I/Os 66 (in 100-pin TQFP) β€”
Pin-to-Pin Propagation Delay (tPD) 7.5 ns (-7 speed grade) β€”
Maximum Internal Counter Frequency 135.1 MHz β€”
Supply Voltage - VCCINT (Core) 3.3 V β€”
Supply Voltage - VCCIO (I/O) 2.5 V or 3.3 V (5.0 V tolerant inputs) β€”
Technology CMOS EEPROM β€”
Package 100-pin TQFP TQFP-100
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
In-System Programming (ISP) Yes, via IEEE 1149.1 JTAG β€”
PCI Compliance PCI Local Bus Specification Revision 2.2 β€”
JTAG Boundary Scan Yes β€”
Lead Free / RoHS Compliant (modern shipments) β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 64
User I/O Pins β€” 66
Usable Gates (min) β€” 600
Usable Gates (typical) β€” 1,250
Pin-to-Pin Delay (tPD) β€” 10 ns
Counter Frequency (fCNT) β€” 227.3 MHz
Supply Voltage (VCCINT) β€” 3.3 V
In-System Programmability β€” Yes (IEEE 1532 / JTAG 1149.1)
Programming Interface β€” 4-pin JTAG (TCK/TMS/TDI/TDO)
RoHS Status β€” Compliant

Datasheets & Resources

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