EPM3064ATC100-7 vs EPM3064ATC100-10 Comparison

Detailed side-by-side comparison of EPM3064ATC100-7 by Altera and EPM3064ATC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064ATC100-7

EPM3064ATC100-7 - MAX 3000A 64-Macrocell CPLD, 7.5ns, 100-TQFP | Altera

EPM3064ATC100-7 Obsolete

Specification Comparison

Parameter EPM3064ATC100-7 EPM3064ATC100-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $3.08 $2.85
Family MAX 3000A MAX 3000A
Usable Gates 1,250 β€”
Macrocells 64 64
Logic Array Blocks (LABs) 2 β€”
Maximum User I/Os 66 (in 100-pin TQFP) β€”
Pin-to-Pin Propagation Delay (tPD) 7.5 ns (-7 speed grade) β€”
Maximum Internal Counter Frequency 135.1 MHz β€”
Supply Voltage - VCCINT (Core) 3.3 V β€”
Supply Voltage - VCCIO (I/O) 2.5 V or 3.3 V (5.0 V tolerant inputs) β€”
Technology CMOS EEPROM β€”
Package 100-pin TQFP TQFP-100 (100-pin Thin Quad Flat Pack)
Mounting Type Surface Mount β€”
Operating Temperature 0C to +70C (commercial) β€”
In-System Programming (ISP) Yes, via IEEE 1149.1 JTAG β€”
PCI Compliance PCI Local Bus Specification Revision 2.2 β€”
JTAG Boundary Scan Yes β€”
Lead Free / RoHS Compliant (modern shipments) β€”
Logic Gates β€” 1250 gates
Logic Array Blocks β€” 2
User I/O Pins β€” 34
Propagation Delay (tPD) β€” 10 ns
Supply Voltage (VCCINT) β€” 3.3 V
Process Technology β€” CMOS EEPROM
In-System Programmability β€” IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant
Global Clock Signals β€” 2 (with optional inversion)
Output Enable Signals β€” 6 or 10 pin- or logic-driven
Output Slew-Rate Control β€” Programmable
Operating Temperature Grade β€” Commercial
MultiVolt I/O Support β€” 1.5V / 1.8V / 2.5V / 3.3V interfaces
RoHS Status β€” [DATA_NEEDED: RoHS compliance]

Datasheets & Resources

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