EPM3064ATC100-7 vs EPM3064ATC100-4 Comparison

Detailed side-by-side comparison of EPM3064ATC100-7 by Altera and EPM3064ATC100-4 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC100-7 EPM3064ATC100-4
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $3.08 $5.20
Family MAX 3000A MAX 3000A
Usable Gates 1,250 1,250 (range 600 to 10,000 across family)
Macrocells 64 β€”
Logic Array Blocks (LABs) 2 2
Maximum User I/Os 66 (in 100-pin TQFP) β€”
Pin-to-Pin Propagation Delay (tPD) 7.5 ns (-7 speed grade) β€”
Maximum Internal Counter Frequency 135.1 MHz β€”
Supply Voltage - VCCINT (Core) 3.3 V β€”
Supply Voltage - VCCIO (I/O) 2.5 V or 3.3 V (5.0 V tolerant inputs) β€”
Technology CMOS EEPROM β€”
Package 100-pin TQFP 100-pin TQFP
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option]
In-System Programming (ISP) Yes, via IEEE 1149.1 JTAG β€”
PCI Compliance PCI Local Bus Specification Revision 2.2 β€”
JTAG Boundary Scan Yes β€”
Lead Free / RoHS Compliant (modern shipments) β€”
Device Type β€” CPLD (EEPROM-based)
Macro Cells β€” 64
Maximum User I/O Pins β€” 34
Pin-to-Pin Delay (tPD) β€” 4.5 ns
Counter Frequency (fCNT) β€” 227.3 MHz
Internal Performance β€” 222.2 MHz
Supply Voltage VCCINT β€” 3.3 V
I/O Voltage (MultiVolt) β€” 2.5 V / 3.3 V / 5.0 V
In-System Programming β€” Yes (IEEE 1149.1 JTAG)
Process Technology β€” CMOS EEPROM
RoHS Status β€” unknown
Architecture β€” 5-level Altera MAX

Datasheets & Resources

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