EPM3064ATC100-7 vs EPM3064ATC100-7N Comparison

Detailed side-by-side comparison of EPM3064ATC100-7 by Altera and EPM3064ATC100-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC100-7 EPM3064ATC100-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $3.08 $6.10
Family MAX 3000A MAX 3000A
Usable Gates 1,250 up to 1,250
Macrocells 64 64
Logic Array Blocks (LABs) 2 2
Maximum User I/Os 66 (in 100-pin TQFP) β€”
Pin-to-Pin Propagation Delay (tPD) 7.5 ns (-7 speed grade) β€”
Maximum Internal Counter Frequency 135.1 MHz β€”
Supply Voltage - VCCINT (Core) 3.3 V β€”
Supply Voltage - VCCIO (I/O) 2.5 V or 3.3 V (5.0 V tolerant inputs) β€”
Technology CMOS EEPROM β€”
Package 100-pin TQFP TQFP-100
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +70C (commercial) 0 Β°C to +70 Β°C (commercial)
In-System Programming (ISP) Yes, via IEEE 1149.1 JTAG β€”
PCI Compliance PCI Local Bus Specification Revision 2.2 β€”
JTAG Boundary Scan Yes β€”
Lead Free / RoHS Compliant (modern shipments) β€”
Device Type β€” CPLD - Complex Programmable Logic Device
User I/O Pins β€” 66
Propagation Delay (tPD) β€” 7.5 ns (pin-to-pin, -7 speed grade)
Maximum Internal Frequency β€” 166.7 MHz (-7 speed grade)
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 3.3 V or 2.5 V
Program Memory Technology β€” EEPROM (non-volatile)
In-System Programming β€” IEEE Std. 1149.1 (JTAG), IEEE Std. 1532
RoHS Status β€” [DATA_NEEDED: confirmed RoHS status from manufacturer page]

Datasheets & Resources

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