EPM3064ATC100-7N vs EPM3064AT100-10N Comparison

Detailed side-by-side comparison of EPM3064ATC100-7N by Altera and EPM3064AT100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064ATC100-7N

EPM3064ATC100-7N - MAX 3000A CPLD, 64 Macrocells, 66 I/O | Altera

EPM3064ATC100-7N Nrnd
Altera
EPM3064AT100-10N

EPM3064AT100-10N - MAX 3000A CPLD, 64 Macrocells, TQFP-100 | Intel

EPM3064AT100-10N Nrnd

Specification Comparison

Parameter EPM3064ATC100-7N EPM3064AT100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $6.10 $5.45
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Macrocells 64 64
Logic Array Blocks (LABs) 2 4
User I/O Pins 66 66
Usable Gates up to 1,250 1,250
Propagation Delay (tPD) 7.5 ns (pin-to-pin, -7 speed grade) β€”
Maximum Internal Frequency 166.7 MHz (-7 speed grade) β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V β€”
Program Memory Technology EEPROM (non-volatile) β€”
In-System Programming IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 β€”
Package TQFP-100 TQFP-100 (T100), 14 mm x 14 mm
Mounting Type Surface Mount β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial) β€”
RoHS Status [DATA_NEEDED: confirmed RoHS status from manufacturer page] [DATA_NEEDED: RoHS compliance status]
Speed Grade β€” -10 (10 ns pin-to-pin delay)
Supply Voltage (VCCINT) β€” 3.3 V
I/O Bank Voltage β€” 3.3 V
5 V Tolerant Inputs β€” Yes (via clamping diodes)
Configuration Memory β€” EEPROM (non-volatile)
Programming Interface β€” JTAG (IEEE Std. 1149.1) with pin-locking
ISP Compliance β€” IEEE Std. 1532
Boundary-Scan Test (BST) β€” IEEE Std. 1149.1 compliant
Operating Temperature (Commercial) β€” 0C to +70C
Lead-Free β€” [DATA_NEEDED: lead-free finish]

Datasheets & Resources

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