EPM3064ATC100-7N vs EPM3064ATC100-10N Comparison

Detailed side-by-side comparison of EPM3064ATC100-7N by Altera and EPM3064ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064ATC100-7N

EPM3064ATC100-7N - MAX 3000A CPLD, 64 Macrocells, 66 I/O | Altera

EPM3064ATC100-7N Nrnd
Altera
EPM3064ATC100-10N

EPM3064ATC100-10N - MAX 3000A CPLD, 64 Macrocells, 66 I/O | Altera

EPM3064ATC100-10N βœ“ Active

Specification Comparison

Parameter EPM3064ATC100-7N EPM3064ATC100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Active
Stock Status In Stock In Stock
Unit Price (USD) $6.10 $2.43
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Macrocells 64 64
Logic Array Blocks (LABs) 2 2
User I/O Pins 66 β€”
Usable Gates up to 1,250 1,250
Propagation Delay (tPD) 7.5 ns (pin-to-pin, -7 speed grade) β€”
Maximum Internal Frequency 166.7 MHz (-7 speed grade) β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V β€”
Program Memory Technology EEPROM (non-volatile) β€”
In-System Programming IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 β€”
Package TQFP-100 100-pin TQFP
Mounting Type Surface Mount Surface Mount
Operating Temperature 0 Β°C to +70 Β°C (commercial) 0C to +70C (commercial)
RoHS Status [DATA_NEEDED: confirmed RoHS status from manufacturer page] Compliant (lead-free)
Maximum User I/O Pins β€” 66
Pin-to-Pin Delay (tPD) β€” 10 ns
Supply Voltage (VCCINT) β€” 3.3 V (3.0 V to 3.6 V)
In-System Programmability β€” Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) β€” Yes - JTAG compliant
Configuration Memory β€” Non-volatile EEPROM
Program/Erase Cycles β€” 100 minimum
MultiVolt I/O β€” Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant

Datasheets & Resources

Browse All Products Create BOM Request Quote