EPM3064ATC100-7N vs EPM3064ATI100-10N Comparison

Detailed side-by-side comparison of EPM3064ATC100-7N by Altera and EPM3064ATI100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC100-7N EPM3064ATI100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Active
Stock Status In Stock In Stock
Unit Price (USD) $6.10 $9.80
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Macrocells 64 64
Logic Array Blocks (LABs) 2 4
User I/O Pins 66 β€”
Usable Gates up to 1,250 1,250
Propagation Delay (tPD) 7.5 ns (pin-to-pin, -7 speed grade) β€”
Maximum Internal Frequency 166.7 MHz (-7 speed grade) 227.3 MHz (counter)
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V β€”
Program Memory Technology EEPROM (non-volatile) β€”
In-System Programming IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 β€”
Package TQFP-100 100-pin TQFP (industrial)
Mounting Type Surface Mount β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial) -40 C to +85 C (industrial)
RoHS Status [DATA_NEEDED: confirmed RoHS status from manufacturer page] RoHS Non-Compliant
Programmable Type β€” In-System Programmable (ISP) via IEEE 1149.1 JTAG
Technology β€” CMOS EEPROM
User I/O β€” 66
Supply Voltage (Core / I/O) β€” 3.3 V
Pin-to-Pin Delay (tPD) β€” 10 ns (-10 speed grade)
JTAG (IEEE 1149.1) β€” Yes
PCI Compliance β€” PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades)
MultiVolt I/O β€” Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing
Lead-Free Status β€” Contains Lead

Datasheets & Resources

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