EPM3064ATC44-10 vs EPM3064ATC44-10N Comparison
Detailed side-by-side comparison of EPM3064ATC44-10 by Altera and EPM3064ATC44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC44-10
EPM3064ATC44-10 - 64-Macrocell MAX 3000A CPLD, TQFP-44 | Altera
EPM3064ATC44-10 ObsoleteAltera
EPM3064ATC44-10N
EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera
EPM3064ATC44-10N β ActiveSpecification Comparison
| Parameter | EPM3064ATC44-10 | EPM3064ATC44-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.35 | $5.10 |
| Family | MAX 3000A | MAX 3000A |
| Logic Elements / Macrocells | 64 macrocells | β |
| Usable Gates | 1,250 | 1250 |
| Number of Logic Blocks / LABs | 4 LABs | β |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Internal Frequency | 227.3 MHz (counter speed) | β |
| Programmable I/Os | 34 | β |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | 3.3 V |
| I/O Bank Voltage (VCCIO) | MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V | β |
| Technology | CMOS EEPROM, 5 V tolerant I/O | β |
| In-System Programming | IEEE Std. 1532 (JTAG) | IEEE Std. 1532 compliant |
| Boundary-Scan Support | IEEE 1149.1 (JTAG) | β |
| Package | TQFP-44, 10 x 10 mm, 0.8 mm pitch | TQFP-44 (10x10 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | 0C to +70C (commercial) | β |
| RoHS Status | Non-compliant (legacy Altera, Pb-bearing) | Compliant |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macro Cells | β | 64 |
| User I/O Pins | β | 34 |
| Logic Array Blocks (LABs) | β | 4 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 192.3 MHz |
| I/O Standard | β | MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) |
| Configuration Memory | β | EEPROM (non-volatile) |
| Boundary-Scan Test | β | IEEE Std. 1149.1 (JTAG) compliant |
| Operating Temperature | β | 0C to +70C (commercial) |
| Pin-Locking | β | Yes (across design iterations) |