EPM3064ATC44-10N vs EPM3064ATC44-7N Comparison

Detailed side-by-side comparison of EPM3064ATC44-10N by Altera and EPM3064ATC44-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064ATC44-10N EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N βœ“ Active

Specification Comparison

Parameter EPM3064ATC44-10N EPM3064ATC44-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $5.10 $2.30
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 1250 1,250
Macro Cells 64 64
User I/O Pins 34 34
Logic Array Blocks (LABs) 4 β€”
Pin-to-Pin Delay (tPD) 10 ns 7.5 ns
Maximum Counter Frequency 192.3 MHz 192.3 MHz (-7 grade)
Supply Voltage (VCCINT) 3.3 V β€”
I/O Standard MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) β€”
Configuration Memory EEPROM (non-volatile) β€”
In-System Programming IEEE Std. 1532 compliant β€”
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) compliant β€”
Package TQFP-44 (10x10 mm) 44-pin TQFP
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +70C (commercial) 0Β°C to +85Β°C (commercial)
RoHS Status Compliant Compliant
Pin-Locking Yes (across design iterations) β€”
Logic Array Blocks β€” 2
Number of Pins β€” 44
Speed Grade β€” -7 (7.5 ns pin-to-pin delay)
Supply Voltage (VCC) β€” 3.3 V
MultiVolt I/O β€” 1.8 V / 2.5 V / 3.3 V
Programmability β€” EEPROM, in-system programmable (ISP)
JTAG Interface β€” IEEE Std. 1149.1 compliant
ISP Standard β€” IEEE Std. 1532 compliant
Boundary-Scan Test (BST) β€” Built-in, JTAG-driven

Datasheets & Resources

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