EPM3064ATC44-10NAF vs EPM3064ALC44-10N Comparison
Detailed side-by-side comparison of EPM3064ATC44-10NAF by Altera and EPM3064ALC44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC44-10NAF
EPM3064ATC44-10NAF - 64-Macrocell MAX 3000A CPLD, 10ns TQFP-44 | Intel
EPM3064ATC44-10NAF NrndAltera
EPM3064ALC44-10N
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N ObsoleteSpecification Comparison
| Parameter | EPM3064ATC44-10NAF | EPM3064ALC44-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.05 | $4.25 |
| Series | MAX 3000A | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 64 | β |
| Logic Elements / LABs | 4 LABs (16 macrocells per LAB) | β |
| Usable Gates | 1250 | 1,250 |
| Number of I/O Pins | 34 | β |
| Propagation Delay (tPD, max) | 10 ns | β |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| I/O Voltage Tolerance | Multi-voltage (3.3 V / 2.5 V / 1.8 V capable) | β |
| Programmable Technology | EEPROM (non-volatile) | β |
| In-System Programmable | Yes (IEEE Std. 1532 compliant) | β |
| Boundary-Scan Test | Yes (IEEE Std. 1149.1 JTAG) | β |
| Pin-Locking | Yes | β |
| Package | TQFP-44 (10x10 mm) | 44-pin PLCC (LC44) |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket compatible) |
| Operating Temperature | [DATA_NEEDED: industrial/commercial grade] | [DATA_NEEDED: commercial / industrial grade] |
| Lead Finish | Lead-free (NiPdAu, AF suffix) | β |
| RoHS Status | Compliant | Compliant |
| Configuration Memory Cycles | 100 erase/program cycles | β |
| Product Family | β | MAX 3000A |
| Macrocells | β | 64 |
| Logic Array Blocks (LABs) | β | 4 |
| User I/O Pins | β | 34 |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 227.3 MHz |
| I/O Bank Voltage (VCCIO) | β | 3.0 V to 3.6 V (MultiVolt) |
| Configuration Memory | β | CMOS EEPROM |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) |
| Open-Drain Output Option | β | Yes (per I/O pin) |
| Output Slew-Rate Control | β | Programmable |