EPM3064ATC44-10NAF vs EPM3064ATC44-10N Comparison

Detailed side-by-side comparison of EPM3064ATC44-10NAF by Altera and EPM3064ATC44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064ATC44-10N EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N - 64-Macro Cell MAX 3000A CPLD | Altera

EPM3064ATC44-10N βœ“ Active

Specification Comparison

Parameter EPM3064ATC44-10NAF EPM3064ATC44-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Active
Stock Status In Stock In Stock
Unit Price (USD) $5.05 $5.10
Series MAX 3000A β€”
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 64 64
Logic Elements / LABs 4 LABs (16 macrocells per LAB) β€”
Usable Gates 1250 1250
Number of I/O Pins 34 β€”
Propagation Delay (tPD, max) 10 ns β€”
Supply Voltage (VCCINT) 3.0 V to 3.6 V 3.3 V
I/O Voltage Tolerance Multi-voltage (3.3 V / 2.5 V / 1.8 V capable) β€”
Programmable Technology EEPROM (non-volatile) β€”
In-System Programmable Yes (IEEE Std. 1532 compliant) β€”
Boundary-Scan Test Yes (IEEE Std. 1149.1 JTAG) IEEE Std. 1149.1 (JTAG) compliant
Pin-Locking Yes Yes (across design iterations)
Package TQFP-44 (10x10 mm) TQFP-44 (10x10 mm)
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: industrial/commercial grade] 0C to +70C (commercial)
Lead Finish Lead-free (NiPdAu, AF suffix) β€”
RoHS Status Compliant Compliant
Configuration Memory Cycles 100 erase/program cycles β€”
Family β€” MAX 3000A
User I/O Pins β€” 34
Logic Array Blocks (LABs) β€” 4
Pin-to-Pin Delay (tPD) β€” 10 ns
Maximum Counter Frequency β€” 192.3 MHz
I/O Standard β€” MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V)
Configuration Memory β€” EEPROM (non-volatile)
In-System Programming β€” IEEE Std. 1532 compliant

Datasheets & Resources

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