EPM3064ATI100-10 vs EPM3064ATC100-10 Comparison
Detailed side-by-side comparison of EPM3064ATI100-10 by Intel and EPM3064ATC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC100-10 - 64-Macrocell MAX 3000A CPLD, 100MHz, TQFP-100 | Altera
EPM3064ATC100-10 NrndSpecification Comparison
| Parameter | EPM3064ATI100-10 | EPM3064ATC100-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.80 | $2.85 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | β |
| Number of Macrocells | 64 | β |
| Number of Logic Array Blocks (LABs) | 4 | β |
| Number of User I/Os | 66 | β |
| Usable Gates | 1,250 | β |
| Supply Voltage | 3.3 V | β |
| Speed Grade | -10 (10 ns pin-to-pin) | β |
| Programmable Type | In-System Programmable (EEPROM) | β |
| Programming Interface | IEEE Std. 1149.1 JTAG | β |
| Package | 100-pin TQFP | TQFP-100 (100-pin Thin Quad Flat Pack) |
| Mounting Type | Surface Mount | β |
| Operating Temperature Grade | Industrial | Commercial |
| Lead Free Status | Contains Lead | β |
| RoHS Status | Non-Compliant | [DATA_NEEDED: RoHS compliance] |
| Logic Gates | β | 1250 gates |
| Macrocells | β | 64 |
| Logic Array Blocks | β | 2 |
| User I/O Pins | β | 34 |
| Propagation Delay (tPD) | β | 10 ns |
| Supply Voltage (VCCINT) | β | 3.3 V |
| Process Technology | β | CMOS EEPROM |
| In-System Programmability | β | IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant |
| Global Clock Signals | β | 2 (with optional inversion) |
| Output Enable Signals | β | 6 or 10 pin- or logic-driven |
| Output Slew-Rate Control | β | Programmable |
| MultiVolt I/O Support | β | 1.5V / 1.8V / 2.5V / 3.3V interfaces |