EPM3064ATI100-10N vs EPM3064ATC100-10 Comparison

Detailed side-by-side comparison of EPM3064ATI100-10N by Altera and EPM3064ATC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATI100-10N EPM3064ATC100-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $9.80 $2.85
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Programmable Type In-System Programmable (ISP) via IEEE 1149.1 JTAG β€”
Technology CMOS EEPROM β€”
Usable Gates 1,250 β€”
Macrocells 64 64
Logic Array Blocks (LABs) 4 β€”
User I/O 66 β€”
Supply Voltage (Core / I/O) 3.3 V β€”
Pin-to-Pin Delay (tPD) 10 ns (-10 speed grade) β€”
Maximum Internal Frequency 227.3 MHz (counter) β€”
Package 100-pin TQFP (industrial) TQFP-100 (100-pin Thin Quad Flat Pack)
Operating Temperature -40 C to +85 C (industrial) β€”
JTAG (IEEE 1149.1) Yes β€”
PCI Compliance PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) β€”
MultiVolt I/O Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing β€”
Lead-Free Status Contains Lead β€”
RoHS Status RoHS Non-Compliant [DATA_NEEDED: RoHS compliance]
Logic Gates β€” 1250 gates
Logic Array Blocks β€” 2
User I/O Pins β€” 34
Propagation Delay (tPD) β€” 10 ns
Supply Voltage (VCCINT) β€” 3.3 V
Process Technology β€” CMOS EEPROM
In-System Programmability β€” IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant
Global Clock Signals β€” 2 (with optional inversion)
Output Enable Signals β€” 6 or 10 pin- or logic-driven
Output Slew-Rate Control β€” Programmable
Operating Temperature Grade β€” Commercial
MultiVolt I/O Support β€” 1.5V / 1.8V / 2.5V / 3.3V interfaces

Datasheets & Resources

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