EPM3064ATI100-10N vs EPM3064ATC100-7N Comparison

Detailed side-by-side comparison of EPM3064ATI100-10N by Altera and EPM3064ATC100-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATI100-10N EPM3064ATC100-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $9.80 $6.10
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Programmable Type In-System Programmable (ISP) via IEEE 1149.1 JTAG β€”
Technology CMOS EEPROM β€”
Usable Gates 1,250 up to 1,250
Macrocells 64 64
Logic Array Blocks (LABs) 4 2
User I/O 66 β€”
Supply Voltage (Core / I/O) 3.3 V β€”
Pin-to-Pin Delay (tPD) 10 ns (-10 speed grade) β€”
Maximum Internal Frequency 227.3 MHz (counter) 166.7 MHz (-7 speed grade)
Package 100-pin TQFP (industrial) TQFP-100
Operating Temperature -40 C to +85 C (industrial) 0 Β°C to +70 Β°C (commercial)
JTAG (IEEE 1149.1) Yes β€”
PCI Compliance PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) β€”
MultiVolt I/O Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing β€”
Lead-Free Status Contains Lead β€”
RoHS Status RoHS Non-Compliant [DATA_NEEDED: confirmed RoHS status from manufacturer page]
User I/O Pins β€” 66
Propagation Delay (tPD) β€” 7.5 ns (pin-to-pin, -7 speed grade)
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 3.3 V or 2.5 V
Program Memory Technology β€” EEPROM (non-volatile)
In-System Programming β€” IEEE Std. 1149.1 (JTAG), IEEE Std. 1532
Mounting Type β€” Surface Mount

Datasheets & Resources

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