EPM3064ATI44-10N vs EPM3064ALC44-10N Comparison
Detailed side-by-side comparison of EPM3064ATI44-10N by Altera and EPM3064ALC44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATI44-10N
EPM3064ATI44-10N - 64-Macrocell 3.3V ISP CPLD | Intel / Altera
EPM3064ATI44-10N ObsoleteAltera
EPM3064ALC44-10N
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N ObsoleteSpecification Comparison
| Parameter | EPM3064ATI44-10N | EPM3064ALC44-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3.95 | $4.25 |
| Family | MAX 3000A | β |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 64 | 64 |
| Usable Gates | 1250 | 1,250 |
| User I/Os | 34 | β |
| Dedicated Inputs | 4 | β |
| Logic Blocks | 4 | β |
| Pin-to-Pin Delay | 10 ns (-10 speed grade) | β |
| Maximum Frequency (fMAX) | 100 MHz | β |
| Programmable Type | In-System Programmable (EEPROM) | β |
| ISP Interface | IEEE Std. 1149.1 (JTAG) | β |
| ISP Standard Compliance | IEEE Std. 1532 | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V (MultiVolt) | β |
| Operating Temperature | -40C to +85C (Industrial, "N" suffix) | [DATA_NEEDED: commercial / industrial grade] |
| Package | 44-pin TQFP | 44-pin PLCC (LC44) |
| Process Technology | CMOS EEPROM | β |
| Boundary-Scan Test | Built-in (JTAG) | β |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket compatible) |
| Lead-Free Status | Contains Lead (per digchip datasheet excerpt) | β |
| RoHS Status | Non-Compliant (per digchip datasheet excerpt) | Compliant |
| Product Family | β | MAX 3000A |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | β | 4 |
| User I/O Pins | β | 34 |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 227.3 MHz |
| Supply Voltage (VCCINT) | β | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | β | 3.0 V to 3.6 V (MultiVolt) |
| Configuration Memory | β | CMOS EEPROM |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) |
| Open-Drain Output Option | β | Yes (per I/O pin) |
| Output Slew-Rate Control | β | Programmable |