EPM3064ATI44-4N vs EPM3064ATI44-10N Comparison
Detailed side-by-side comparison of EPM3064ATI44-4N by Altera and EPM3064ATI44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3064ATI44-4N | EPM3064ATI44-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.25 | $3.95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Logic Elements / Macrocells | 64 macrocells | β |
| Usable Gates | 1,250 gates | 1250 |
| Number of Logic Array Blocks (LABs) | 4 LABs (16 macrocells each) | β |
| Maximum Operating Frequency | 222.2 MHz | β |
| Pin-to-Pin Propagation Delay (tPD) | 4.5 ns (-4 speed grade) | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V | β |
| User I/O Pins | 34 I/O | β |
| Package | 44-pin TQFP | 44-pin TQFP |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (Industrial, "N" suffix) |
| Programming Interface | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 ISP | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: rohs status] | Non-Compliant (per digchip datasheet excerpt) |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 64 |
| User I/Os | β | 34 |
| Dedicated Inputs | β | 4 |
| Logic Blocks | β | 4 |
| Pin-to-Pin Delay | β | 10 ns (-10 speed grade) |
| Maximum Frequency (fMAX) | β | 100 MHz |
| Programmable Type | β | In-System Programmable (EEPROM) |
| ISP Interface | β | IEEE Std. 1149.1 (JTAG) |
| ISP Standard Compliance | β | IEEE Std. 1532 |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V or 2.5 V (MultiVolt) |
| Process Technology | β | CMOS EEPROM |
| Boundary-Scan Test | β | Built-in (JTAG) |
| Lead-Free Status | β | Contains Lead (per digchip datasheet excerpt) |