EPM3064ATI44-7N vs EPM3064ATC44-7N Comparison

Detailed side-by-side comparison of EPM3064ATI44-7N by Altera and EPM3064ATC44-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATI44-7N EPM3064ATC44-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $5.10 $2.30
Family MAX 3000A MAX 3000A
Logic Elements / Macrocells 64 macrocells β€”
Usable Gates 1,250 gates 1,250
Maximum Frequency (fMAX) 135.1 MHz β€”
Pin-to-Pin Logic Delay 7 ns (speed grade -7) β€”
User I/O Count 34 I/O β€”
Dedicated Input Pins 4 β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Bank Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5 V tolerant (multiVolt) β€”
Program Memory Type EEPROM (in-system programmable) β€”
Programming Interface IEEE 1149.1 JTAG β€”
Package 44-pin TQFP (10x10 mm, 0.8 mm pitch) 44-pin TQFP
Operating Temperature Grade Industrial (-40C to +85C) β€”
RoHS Status Compliant (lead-free, 'N' suffix) Compliant
Process Technology 0.30 Β΅m CMOS EEPROM β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 64
Logic Array Blocks β€” 2
User I/O Pins β€” 34
Number of Pins β€” 44
Speed Grade β€” -7 (7.5 ns pin-to-pin delay)
Pin-to-Pin Delay (tPD) β€” 7.5 ns
Maximum Counter Frequency β€” 192.3 MHz (-7 grade)
Supply Voltage (VCC) β€” 3.3 V
MultiVolt I/O β€” 1.8 V / 2.5 V / 3.3 V
Programmability β€” EEPROM, in-system programmable (ISP)
JTAG Interface β€” IEEE Std. 1149.1 compliant
ISP Standard β€” IEEE Std. 1532 compliant
Boundary-Scan Test (BST) β€” Built-in, JTAG-driven
Operating Temperature β€” 0Β°C to +85Β°C (commercial)
Mounting Type β€” Surface Mount

Datasheets & Resources

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