EPM3128AFC256-7N vs EPM3256AFC256-10N Comparison
Detailed side-by-side comparison of EPM3128AFC256-7N by Altera and EPM3256AFC256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128AFC256-7N
EPM3128AFC256-7N - 128-Macro 7.5ns MAX 3000A CPLD | Altera
EPM3128AFC256-7N Nrnd
Specification Comparison
| Parameter | EPM3128AFC256-7N | EPM3256AFC256-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.85 | $25.95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based MAX | β |
| Macro Cells | 128 | β |
| Usable Gates | 2,500 | 5,000 gates |
| User I/Os | 98 | β |
| Propagation Delay (tPD) | 7.5 ns | β |
| Internal fMAX | 192.3 MHz | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V | β |
| Logic Family | CMOS | CMOS |
| Programmability | In-system (ISP), IEEE Std. 1532, JTAG (IEEE Std. 1149.1) | EEPROM, in-system programmable (ISP) |
| Package | 256-BGA (FineLine, FBGA) | 256-pin FineLine BGA |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to 70 C (commercial) |
| Mounting Type | Surface Mount | β |
| Macrocells | β | 256 |
| Maximum User I/O | β | 161 |
| Pin-to-Pin Logic Delay | β | 10 ns |
| Maximum Counter Frequency | β | 227.3 MHz |
| Core Voltage | β | 3.3 V |
| I/O Logic Level Compatibility | β | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| JTAG Interface | β | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) |
| PCI Compliance | β | PCI Local Bus Specification Rev 2.2 (at -10 grade) |