EPM3128ATC100-7 vs EPM3128ATI100-10 Comparison
Detailed side-by-side comparison of EPM3128ATC100-7 by Intel and EPM3128ATI100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3128ATC100-7
EPM3128ATC100-7 - MAX 3000A CPLD, 128 Macro Cells, 100-TQFP | Intel
EPM3128ATC100-7 ObsoleteAltera
EPM3128ATI100-10
EPM3128ATI100-10 - 128-Macro MAX 3000A CPLD, 10ns TQFP-100 | Altera
EPM3128ATI100-10 β ActiveSpecification Comparison
| Parameter | EPM3128ATC100-7 | EPM3128ATI100-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.20 | $8.40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| Typical Gates | 2500 | β |
| User I/Os | 80 | 80 |
| Logic Elements / LABs | 4 Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] |
| Propagation Delay (tPD) | 7.5 ns | β |
| Counter Frequency (fCNT) | 129.9 MHz | up to 227.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Voltage Tolerance | 5.0 V tolerant inputs | β |
| Programming Technology | EEPROM (non-volatile, in-system programmable) | β |
| ISP Standard | IEEE Std. 1532 (JTAG) | β |
| Package | 100-pin TQFP, 14x14 mm, 0.5 mm pitch | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Operating Temperature | 0C to +70C (Commercial) | -40 Β°C to +85 Β°C (industrial) |
| Speed Grade | -7 (fastest grade in family) | β |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Usable Gates | β | 2,500 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| MultiVolt I/O Levels | β | 5.0 V / 3.3 V / 2.5 V compatible |
| Programmability | β | EEPROM, 3.3 V in-system (JTAG) |
| Open-Drain Output Option | β | Yes (per I/O pin) |
| Boundary-Scan (JTAG) | β | IEEE 1149.1 compliant |
| Mounting Type | β | Surface Mount |