EPM3128ATC144-7 vs EPM3128ATC144-7N Comparison
Detailed side-by-side comparison of EPM3128ATC144-7 by Intel and EPM3128ATC144-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128ATC144-7N - MAX 3000A CPLD, 128 Macrocells, 7.5ns | Altera
EPM3128ATC144-7N β ActiveSpecification Comparison
| Parameter | EPM3128ATC144-7 | EPM3128ATC144-7N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.10 | $9.25 |
| Family | MAX 3000A | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | β |
| Usable Gates | 2,500 | β |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | β |
| User I/Os | 96 | 96 |
| Package | TQFP-144 (22x22 mm) | TQFP-144 (20 x 20 mm, 0.5 mm pitch) |
| Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (multiVolt) | β |
| Speed Grade | -7 | β |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns | β |
| Maximum Internal Frequency (fCNT) | 129.9 MHz | β |
| Programming Technology | CMOS EEPROM (in-system programmable) | β |
| JTAG Support | IEEE 1149.1 boundary-scan + ISP | β |
| Operating Temperature | 0C to +70C (Commercial) | 0 Β°C to +70 Β°C (commercial) |
| Mounting Type | Surface Mount | Surface Mount (SMD/SMT) |
| Process Technology | CMOS EEPROM | β |
| Series | β | MAX 3000A |
| Architecture | β | EEPROM-based, MAX architecture |
| Number of Macrocells | β | 128 |
| Number of Usable Gates | β | Up to 10,000 |
| Pin Count | β | 144 |
| Logic Family | β | CMOS |
| Propagation Delay (tPD) | β | 7.5 ns (pin-to-pin, -7 speed grade) |
| Counter Frequency | β | Up to 227.3 MHz |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| In-System Programmability (ISP) | β | Yes, via JTAG (IEEE 1149.1) |
| PCI Compliance | β | Compatible with PCI Local Bus Specification Rev. 2.2 |
| RoHS Status | β | Lead-free (-7N suffix indicates Pb-free finish) |