EPM3128ATC144-7N vs EPM3256ATC144-7N Comparison
Detailed side-by-side comparison of EPM3128ATC144-7N by Altera and EPM3256ATC144-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128ATC144-7N - MAX 3000A CPLD, 128 Macrocells, 7.5ns | Altera
EPM3128ATC144-7N β Active
Specification Comparison
| Parameter | EPM3128ATC144-7N | EPM3256ATC144-7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.25 | $17.20 |
| Series | MAX 3000A | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Architecture | EEPROM-based, MAX architecture | β |
| Number of Macrocells | 128 | β |
| Number of Usable Gates | Up to 10,000 | β |
| User I/Os | 96 | 116 |
| Pin Count | 144 | β |
| Package | TQFP-144 (20 x 20 mm, 0.5 mm pitch) | 144-pin TQFP |
| Logic Family | CMOS | CMOS |
| Propagation Delay (tPD) | 7.5 ns (pin-to-pin, -7 speed grade) | 7.5 ns |
| Counter Frequency | Up to 227.3 MHz | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | β |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | 0C to +70C (Commercial) |
| In-System Programmability (ISP) | Yes, via JTAG (IEEE 1149.1) | β |
| PCI Compliance | Compatible with PCI Local Bus Specification Rev. 2.2 | β |
| Mounting Type | Surface Mount (SMD/SMT) | Surface Mount |
| RoHS Status | Lead-free (-7N suffix indicates Pb-free finish) | Compliant |
| Family | β | MAX 3000A |
| Macro Cells | β | 256 |
| Logic Gates (usable) | β | 5,000 |
| Number of Logic Array Blocks (LABs) | β | 16 |
| Maximum Internal Frequency | β | 126.6 MHz |
| Supply Voltage (VCCIO) | β | 3.0 V to 3.6 V |
| Programmable Logic Technology | β | CMOS EEPROM-based |
| In-System Programmable (ISP) | β | Yes (3.3 V) |
| JTAG Support | β | IEEE 1149.1 boundary-scan |