EPM3128ATI144-10N vs EPM3128ATC144-7N Comparison
Detailed side-by-side comparison of EPM3128ATI144-10N by Intel and EPM3128ATC144-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3128ATI144-10N
EPM3128ATI144-10N - 128-Macrocell MAX 3000A CPLD, 10ns | Intel / Altera
EPM3128ATI144-10N NrndAltera
EPM3128ATC144-7N - MAX 3000A CPLD, 128 Macrocells, 7.5ns | Altera
EPM3128ATC144-7N β ActiveSpecification Comparison
| Parameter | EPM3128ATI144-10N | EPM3128ATC144-7N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.32 | $9.25 |
| Family | MAX 3000A | β |
| Logic Type | CMOS EEPROM-based CPLD | β |
| Macrocells | 128 | β |
| Typical Gates | 2.5K | β |
| User I/Os | 96 | 96 |
| Propagation Delay (tPD) | 10 ns | 7.5 ns (pin-to-pin, -7 speed grade) |
| Maximum Internal Frequency | 98 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| Output Bank Voltage (VCCIO) | 3.3 V or 2.5 V | β |
| Package | 144-pin TQFP | TQFP-144 (20 x 20 mm, 0.5 mm pitch) |
| Mounting Type | Surface Mount | Surface Mount (SMD/SMT) |
| Operating Temperature | Industrial -40C to +85C | 0 Β°C to +70 Β°C (commercial) |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | β |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) | β |
| Configuration Memory | Non-volatile EEPROM | β |
| RoHS Status | Compliant | Lead-free (-7N suffix indicates Pb-free finish) |
| Series | β | MAX 3000A |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Architecture | β | EEPROM-based, MAX architecture |
| Number of Macrocells | β | 128 |
| Number of Usable Gates | β | Up to 10,000 |
| Pin Count | β | 144 |
| Logic Family | β | CMOS |
| Counter Frequency | β | Up to 227.3 MHz |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| In-System Programmability (ISP) | β | Yes, via JTAG (IEEE 1149.1) |
| PCI Compliance | β | Compatible with PCI Local Bus Specification Rev. 2.2 |