EPM3128ATI144-5N vs EPM3128ATC144-5N Comparison
Detailed side-by-side comparison of EPM3128ATI144-5N by Altera and EPM3128ATC144-5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128ATI144-5N
EPM3128ATI144-5N - 128-Macrocell 2.5K CPLD MAX 3000A | Altera
EPM3128ATI144-5N NrndAltera
EPM3128ATC144-5N
EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera
EPM3128ATC144-5N β Last Time BuySpecification Comparison
| Parameter | EPM3128ATI144-5N | EPM3128ATC144-5N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.50 | $13.75 |
| Family | MAX 3000A | MAX 3000A |
| Logic Gates | 2,500 gates | β |
| Macro Cells | 128 | β |
| User I/Os | 96 | β |
| Maximum Operating Frequency | 192.3 MHz | β |
| Pin-to-Pin Propagation Delay (tPD) | 5.0 ns | β |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | β |
| I/O Standard | LVCMOS / LVTTL (5.0 V tolerant inputs) | β |
| Programming Interface | JTAG (IEEE 1149.1 BST) - in-system | β |
| Process Technology | 0.30 um CMOS EEPROM | β |
| Configuration Memory | Non-volatile on-chip EEPROM | β |
| Package | TQFP-144 (20x20 mm, 0.5 mm pitch) | 144-pin TQFP (20x20 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40C to +85C (industrial) | 0C to 70C (Commercial) |
| MSL Level | 3 (168 hours) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free) |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Device Type | β | CPLD - Complex Programmable Logic Device |
| Logic Family | β | CMOS |
| Macrocells | β | 128 |
| Usable Gates | β | 2500 |
| User I/O | β | 96 |
| Pin-to-Pin Logic Delay | β | 5 ns |
| Counter Frequency | β | up to 227.3 MHz |
| Supply Voltage (Core) | β | 3.3 V |
| I/O Logic Levels Supported | β | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| In-System Programmability | β | Yes (3.3-V via JTAG) |
| JTAG Boundary Scan | β | IEEE Std 1149.1 compliant |