EPM3256AFC256-10 vs EPM3256AFC256-10N Comparison

Detailed side-by-side comparison of EPM3256AFC256-10 by Altera and EPM3256AFC256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256AFC256-10 EPM3256AFC256-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $19.95 $25.95
Family MAX 3000A MAX 3000A
Logic Family CMOS (EEPROM-based) CMOS
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 256 β€”
Usable Gates 5,000 5,000 gates
Logic Array Blocks (LABs) 16 (16 macrocells each) β€”
Maximum User I/Os 161 β€”
Propagation Delay (tPD) 10 ns β€”
Internal Counter Frequency (fCNT) 95.2 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Voltage Tolerance 5.0 V tolerant β€”
In-System Programmability Yes (3.3 V ISP via JTAG IEEE 1149.1) β€”
Operating Temperature 0Β°C to +70Β°C (Commercial) 0 C to 70 C (commercial)
Package 256-ball FBGA (Fine-Line BGA) 256-pin FineLine BGA
Pitch [DATA_NEEDED: BGA ball pitch] β€”
Mounting Type Surface Mount β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] β€”
Macrocells β€” 256
Maximum User I/O β€” 161
Pin-to-Pin Logic Delay β€” 10 ns
Maximum Counter Frequency β€” 227.3 MHz
Core Voltage β€” 3.3 V
I/O Logic Level Compatibility β€” 5.0 V / 3.3 V / 2.5 V (MultiVolt)
Programmability β€” EEPROM, in-system programmable (ISP)
JTAG Interface β€” IEEE 1532 / JTAG (TDI, TDO, TMS, TCK)
PCI Compliance β€” PCI Local Bus Specification Rev 2.2 (at -10 grade)

Datasheets & Resources

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