EPM3256AFC256-10N vs EPM3256AQC208-10N Comparison

Detailed side-by-side comparison of EPM3256AFC256-10N by Altera and EPM3256AQC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256AFC256-10N EPM3256AQC208-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $25.95 $4.62
Family MAX 3000A β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Usable Gates 5,000 gates 10,000
Macrocells 256 β€”
Maximum User I/O 161 β€”
Pin-to-Pin Logic Delay 10 ns β€”
Maximum Counter Frequency 227.3 MHz 227.3 MHz
Core Voltage 3.3 V β€”
I/O Logic Level Compatibility 5.0 V / 3.3 V / 2.5 V (MultiVolt) β€”
Programmability EEPROM, in-system programmable (ISP) β€”
JTAG Interface IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) β€”
Package 256-pin FineLine BGA β€”
Logic Family CMOS β€”
PCI Compliance PCI Local Bus Specification Rev 2.2 (at -10 grade) β€”
Operating Temperature 0 C to 70 C (commercial) 0C to +70C (Commercial)
Series β€” MAX 3000A
Programmable Type β€” In-System Programmable (EEPROM)
Number of Macrocells β€” 256
Number of Logic Elements/Blocks β€” 16 LABs
Number of I/O Pins β€” 161 (158 user I/O per Arrow listing)
Propagation Delay (tpd) β€” 10 ns (max)
Supply Voltage - Internal β€” 3.0 V to 3.6 V (3.3 V typical)
Package / Case β€” 208-BFQFP / 208-PQFP (28x28 mm)
Mounting Type β€” Surface Mount
ISP Compliance β€” IEEE Std. 1532
Boundary Scan β€” IEEE Std. 1149.1 (JTAG)
I/O Tolerance β€” 5 V tolerant, MultiVolt interface
RoHS Status β€” [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data]

Datasheets & Resources

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