EPM3256AFC256-10N vs EPM3512AFC256-10 Comparison
Detailed side-by-side comparison of EPM3256AFC256-10N by Altera and EPM3512AFC256-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3256AFC256-10N | EPM3512AFC256-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.95 | $17.50 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 5,000 gates | 10,000 |
| Macrocells | 256 | 512 |
| Maximum User I/O | 161 | β |
| Pin-to-Pin Logic Delay | 10 ns | β |
| Maximum Counter Frequency | 227.3 MHz | 87 MHz |
| Core Voltage | 3.3 V | β |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | β |
| Programmability | EEPROM, in-system programmable (ISP) | β |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | β |
| Package | 256-pin FineLine BGA | 256-pin FBGA |
| Logic Family | CMOS | β |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | β |
| Operating Temperature | 0 C to 70 C (commercial) | β |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum I/O Pins | β | 208 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Voltage Tolerance | β | 5-V tolerant |
| Programmable Technology | β | CMOS EEPROM |
| In-System Programmability | β | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| Operating Temperature Range | β | [DATA_NEEDED: industrial/commercial operating temperature range] |
| Pin Count | β | 256 |
| Mounting Type | β | Surface Mount |
| RoHS Status | β | unknown |
| Architecture | β | MAX (Multiple Array matriX) EEPROM-based |